1. Field of the Invention
The present invention relates to a semiconductor package in which adverse effects associated with by noise is reduced by absorbing the noise.
2. Description of the Related Art
FIG. 1 is a sectional view of a conventional semiconductor package where numeral 11 designates a resin-sealed type semiconductor package, numeral 12 designates a die pad, numeral 14 designates a lead, numeral 16 designates a semiconductor chip and numeral 18 designates a bonding wire for connecting pads formed on the surface of the semiconductor chip 16 to the leads 14. Numeral 20 designates a mold resin for sealing the die pad 12, the semiconductor chip 16, the bonding wire 18 and the like thereby preventing moisture outside the package 11 from invading into the inside of the semiconductor package 11 and protecting the semiconductor chip 16 and the like against impacts. Numeral 34 designates a die bonding resin for die-bonding the semiconductor chip 16 onto the die pad 12.
Next, an explanation will be given of the operation of the conventional semiconductor package illustrated by FIG. 1.
The semiconductor chip 16 is an individual semiconductor chip which has been obtained by dividing a wafer after a wafer production process. The semiconductor chip 16 is fixed on the die pad 12 by the die bonding resin 34. Next, the electrode pads formed on the surface of the semiconductor chip 16 are connected to the leads 14 by the bonding wires 18 through the wire bonding process. Thereafter, the die pad 12, the semiconductor chip 16, the bonding wires 18 and the like are sealed by the mold resin 20 whereby the fabrication process of the semiconductor package 11 is completed.
The back face of the semiconductor chip 16 is fixed to the inside of the semiconductor package 11 by being adhered onto the die pad 12 by the die bonding resin 34. The electrode pads formed on the surface of the semiconductor chip 16 are electrically connected to the corresponding leads 14 by the bonding wires 18.
The semiconductor package 11 is mounted on a printed circuit board, not illustrated, by soldering portions (outer leads) of the leads 14 which project out to the outside of the semiconductor package 11, to wirings of the printed circuit board and thereafter, integrated to various electrical devices.
The semiconductor chip 16 receives power supplied from wirings (for example, printed wiring) of the printed circuit board, and inputs or outputs various signals such as data or control signals to or from outside integrated circuit devices (such as IC, LSI and the like), display devices (such as LCD) or the like via the printed wirings.
The current path between the semiconductor chip 16 and the printed wiring on a printed circuit board, is constituted by the printed wiring--the lead 14--the bonding wire 18--the electrode pad--the semiconductor chip 16.
The mold resin 20 seals the die pad 12, the leads 14, the semiconductor chip 16, the bonding wires 18 and the like except portions of the leads 14 (outer lead) projected to the outside of the semiconductor package 11 thereby protecting the semiconductor package 11 such that no moisture or no water invades from the outside, and protects against impacts applied from the outside.
The handling of the semiconductor chip 16 is facilitated by sealing it to the inside of the semiconductor package 11 since it is protected against the influence of outside moisture or impact which gives rise to an effect by which the mounting of the semiconductor chip 16 onto a printed circuit board that is mounted to various electric devices, is facilitated.
The conventional semiconductor package 11 with the above-described configuration has the following drawback.
With respect to the semiconductor chip 16, formation of a further fine structures in the tendency with higher integration for the purposes of high capability, high function, low cost and the like. With the formation of fine structures, erroneous operation of the semiconductor chip 16 caused by noise introduced from the outside or adverse effect on external circuits due to noise generated at the inside of the semiconductor chip 16, is becoming cumbersome.
It is considered that the cause of such a noise problem is that, since parasitic capacitances produced in forming to integrate transistors at the inside of the semiconductor chip 16, or the capacitances of capacitors formed on the surface of the semiconductor chip 16, are reduced with the formation of a fine structure of the design rule and accordingly, noise derived from the outside or noise generated at the inside of the chip cannot be absorbed by these capacitors.
A plurality of transistors integrated at the inside of the semiconductor chip 16 are operated by clocks. The clock is supplied from the outside of the semiconductor package 11, or the clock is generated by using an oscillator, or the clock is formed by a method of oscillation using a CR circuit, or the like. Such a clock is supplied to a plurality of circuits comprising transistors.
When the level of the clock is changed (rise or fall), the transistor is turned on or off and accordingly, a penetrating current flows from a power supply to the ground whereby the level of the power supply voltage is fluctuated. The fluctuation of the power supply voltage constitutes a noise that is generated from the inside of the semiconductor chip 16.
With respect to a semiconductor chip in the past generation where the design rule of the transistor was large, parasitic capacitances of transistors or capacitances of capacitors formed at the inside of transistors are large and therefore, the fluctuation of the power supply voltage can be absorbed by the parasitic capacitances of transistors or capacitors formed at the inside of the semiconductor chip.
However, when the design rule becomes small with higher integration and fine structure formation of a semiconductor integrated circuit device, the parasitic capacitances of transistors are reduced and the capacitances of capacitors formed at the inside of the semiconductor chip are getting smaller since the area thereof is reduced and accordingly, the fluctuation of the power supply voltage cannot be absorbed by the parasitic capacitances of transistors or the capacitors formed at the inside of the semiconductor chip.
Further, with the reduction in the design rule, transistors are operated at a higher speed whereby further fluctuation of the power supply voltage is produced and as a result, further noise is caused.
When noise (hereinafter, referred to as "power supply noise") is superposed on the power supply voltage supplied from the outside of the package via printed wirings or the like, the power supply voltage supplied to the semiconductor chip 16 is fluctuated whereby erroneous operation is caused. When the design rule is large, such a power supply noise can be absorbed by the parasitic capacitances of transistors or the capacitances of capacitors formed at the inside of the semiconductor chip. However, with the reduction in the design rule, the power supply noise cannot be absorbed by the reason described above.